ADSP-214xx SHARC Processor Hardware Reference A-191
Registers Reference
Precision Clock Generator Registers
The precision clock generator (PCG) consists of four identical units. Each
of these units (A, B, C, and D) generates one clock (CLKA_O CLKB_O,
CLKC_O or CLKD_O) and one frame sync (FSA_O, FSB_O, FSC_O or FSD_O)
output.
Control Registers (PCG_CTLxy)
Two control registers (y=0, 1) operate for each unit. The control registers
enable clocks, frame syncs, and select divisors for each unit. These regis-
ters are shown in Figure A-101 and Figure A-102 and described in
Table A-98 and Table A-99. Note the different units (x = A, B, C, D) any
clock unit can be chosen.
Table A-97. SRCRATx Register Bit Descriptions (RO)
Bit Name Description
14–0 SRCx_RATIO Sampling Ratio of Frame Syncs. These bits can be read to find
the ratio of output to input sampling frequency
(SRCx_FS_OP_I/SRCx_FS_IP_I). This ratio is reported in
4.11 (integer.fraction) format where the 15-bit value of the
normal binary number is comprised of 4 bits for the integer
and 11 bits for the fraction.
15 SRCx_MUTEOUT
Mute Status. The SRCx_MUTEOUT bits in SRCRATx regis-
ter report the status of the MUTE_OUT signal. Once the
SRCx_MUTEOUT signal is cleared then the ratio can be read.
When the SRCx_ENABLE is set or there is a change in the
sample ratio, the MUTE_OUT signal is asserted. The
MUTE_OUT signal remains asserted until the digital servo
loop's internal fast settling mode is complete. When the digital
servo loop has switched to slow settling mode, the
MUTE_OUT signal is deasserted. Reset = 0x80008000.
30–16 SRCy_RATIO Sampling Ratio of Frame Syncs. See bits 14–0.
31 SRCy_MUTEOUT Mute Status. See bit 15.
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