ADSP-214xx SHARC Processor Hardware Reference 10-21
Serial Ports
Operation Modes
SPORTs operate in five modes:
• Standard serial mode, described in “Standard Serial Mode” on
page 10-25
• Left-justified mode, described in “Left-Justified Mode” on
page 10-28
•I
2
S mode, described in “I2S Mode” on page 10-30
• Packed mode, described in “Packed Mode” on page 10-37
• Multichannel mode, described in “Multichannel Mode” on
page 10-31
Bit names and their functionality change based on the SPORT
operating mode. See the mode specific section for the bit names
and their functions.
Pairings of SPORTs (0 and 1, 2 and 3, 4 and 5 and 6 and 7) are
only used in loopback mode for testing.
The main control register for each serial port is the serial port control reg-
ister, SPCTLx. These registers are described in“Serial Port Registers” on
page A-150.
When changing operating modes, clear the serial port control regis-
ter before the new mode is written to the register.
The
SPCTLx registers control the operating modes of the serial ports.
Table 10-6 lists all the bits in the
SPCTLx register.
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