Peripheral Registers
A-100 ADSP-214xx SHARC Processor Hardware Reference
Synchronous Base Address Register (MLB_SBCR)
The MLB_SBCR, described in Table A-62, holds the base address of the sys-
tem memory buffers of all synchronous channels in the device.
Asynchronous Base Address Register (MLB_ABCR)
The MLB_ABCR register, described in Table A-63, holds the base address of
the system memory buffers of all asynchronous channels in the device.
Table A-62. MLB_SBCR Register Bit Descriptions (RW)
Bit Name Description
4–0 STBA Synchronous transmit base address for DMA mode
15–5 Reserved
20–16 SRBA Synchronous receive base address for DMA mode
31–21 Reserved
Table A-63. MLB_ABCR Register Bit Descriptions (RW)
Bit Name Description
4–0 ATBA Asynchronous transmit base address for DMA mode
15–5 Reserved
20–16 ARBA Asynchronous receive base address for DMA mode
31–21 Reserved
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