ADSP-2146x External Port Registers
A-22 ADSP-214xx SHARC Processor Hardware Reference
Table A-9. AMICTLx Register Bit Descriptions (RW)
Bit Name Description
0AMIENAMI Enable.
0 = AMI is disabled
1 = AMI is enabled
2–1 Reserved
3PKDISDisable Packing/Unpacking.
0 = 8-bit data received packed to 32-bit data. Similarly, 32-bit data
to be transmitted is unpacked to four 8-bit data.
1 = 8-bit data received zero-filled, for transmitted data only 8-bit
LSB part of the 32-bit data is written to external memory.
Note this bit should not be set for bank 0 which is to be used for
instruction fetch
4MSWFMost Significant Word First. Applicable only with packing disabled
(PKDIS=0).
0 = 1st 8-bit word read/write occupies the least significant position
in the 32-bit packed word.
1 = 1st 8-bit word read/write occupies the most significant position
in the 32-bit packed word.
5ACKENEnable the ACK Pin.
If enabled, reads/writes to devices have to be extended by the corre-
sponding devices by pulling ACK low. When ACKEN is set then
the ACK pin is sampled after the waitstate value is programmed.
10–6 WS Wait States.
00000 = Reserved (wait state value of 32 if used)
00001 = Reserved
00010 = wait state = 2
11111 = Wait state = 31
13–11 HC Bus Hold Cycle at the End of Write Access.
000 = Disable bus hold cycle
001 = Hold address for one external port clock cycle
010 = Hold address for two external port clock cycles
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