ADSP-214xx SHARC Processor Hardware Reference I-13
Index
IDP bits (continued)
IDP_DMA_EN bit
do not set, 11-16
monitor number of samples
(IDP_NSET), A-176
PDAP clock edge
(IDP_PDAP_CLKEDGE), 11-27,
A-181
PDAP enable (IDP_PDAP_EN), 11-29,
A-181
PDAP input mask bits, 11-27
PDAP packing mode
(IDP_PDAP_PACKING), A-181
PDAP reset (IDP_PDAP_RESET),
A-181
ping-pong DMA enable (IDP_PING)
bits, A-178
port select (IDP_PORT_SELECT),
A-180
port select (IDP_PP_SELECT), 11-27
reset (IDP_PDAP_RESET) bit, A-181
IDP_CTL0 (input data port control)
register, 11-29, A-175
IDP_CTL1 (input data port control)
register, 11-28, A-177, A-178
IFS (internal frame sync select) bit, A-155,
A-164
IIR
global control register (IIRCTL1), A-87
IIR accelerator
32- to 40-bit packing, 6-62
chained DMA, 2-17
chain pointer DMA, 6-62
coefficient memory, 6-60
control (IIRCTLx) register, 6-55
data memory, 6-60
debugging, 6-65
DMA status (IIRDMASTAT) register,
6-56
DMA transfers, 6-62
IIR accelerator (continued)
floating-point operations, 6-59
internal memory, 6-60
MAC unit, 6-59
operating modes, 6-61
single step, 6-65
throughput, 6-67
transposed form 2 biquad, 6-58
IIR accelerator registers
debug mode control (IIRDEBUGCTL),
6-55
DMA status (IIRDMASTAT), 6-55
global control (IIRCTLx), 6-55
MAC status (IIRMACSTAT), 6-56
IIR bits
40-bit floating-point select
(IIR_FORTYBIT), A-89
enable (IIR_EN),
A-87
II
SPx (serial port DMA internal index)
registers, 2-4, 2-25
IMSPI (serial peripheral interface address
modify) register, 15-32
IMSPx (SPORT DMA address modifier)
registers, 2-5, 2-25
index registers, 2-27
INDIV (input divisor) bit, A-8, A-13
input setup and hold time, 23-36
input signal conditioning, 23-33
input slave select enable (ISSEN) bit,
15-26, A-233
input synchronization delay, 23-30
INTEN (DMA interrupt enable) bit, 15-26
interconnections, master-slave, 15-3
interleaving 16-bit addressing, DDR2,
3-65
internal index, 2-27
internal memory
DMA index (IDP_DMA_Ix) registers,
11-20, 11-21
DMA index (IISPx) registers, 2-4, 2-25
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