Analog Devices SHARC ADSP-214 Series - Page 377

ADSP-214xx SHARC Processor Hardware Reference 7-9
Pulse Width Modulation
The resulting on-times (active low) of the PWM signals over the full
PWM period (two half periods) produced by the PWM timing unit and
illustrated in Figure 7-2 may be written as:
The range of T
AH
is:
and the corresponding duty cycles are:
Figure 7-2. Center-Aligned Paired PWM in Single Update Mode,
Low Polarity
......................
.....
......................
.....
PWMPERIOD
PWMPERIOD
PWMCHA
PWMCHA
PWMPERIOD
2
+
0
PWMPERIOD
2
PWMPERIOD
2
+
0
2xPWMDT 2xPWMDT
count
PWM_AH
PWM_AL
PWMPHASE
PWM INTERRUPT
LATCH BIT
02– PWMPERIOD t
PCLK
]××[
T
AH
PWMPERIOD 2 PWMCHA PWMDT)+(× t
PCLK
×–(=
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