ADSP-214xx SHARC Processor Hardware Reference 3-107
External Port
the internal count register (
ICEPx), and is the same for every tap. The
read/write pointer in external index register (EIEPx) serves as the index
address for these read/writes.
TL[N] is the first tap list entry in the internal memory as pointed by the
TPEP, the tap list pointer. The tap list entries are 27-bit signed integers.
Therefore, for each read/write block, the DMA state machine fetches the
offset from the tap list. The offset is added to the EIEP value to get the
start address of the next block. The external addresses are circular buffered
if circular buffering is enabled (Figure 3-26, Figure 3-27).
Once the ICEP register for the final tap decrements to zero (both TCEP and
ICEP are zero), then the tap list DMA access is complete and the DMA
completion interrupt is generated (if chaining is enabled the interrupt
depends on the PCI bit setting).
The write back mode (WRBEN bit) is not applicable for tap list based DMA
(as the addressing is pre-modify, and therefore the EIEP value coincides
with the TCB value even at the end of DMA). So even if the WRBEN bit is
set in tap list DMA mode, the write backs do not occur.
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