Analog Devices SHARC ADSP-214 Series - Page 99

ADSP-214xx SHARC Processor Hardware Reference 2-21
I/O Processor
The order the descriptors are fetched for scatter/gather DMA with circular
buffering enabled is shown in Table 2-25 and Table 2-26.
Table 2-25. External Port TCBs for Scatter/Gather DMA
Address Register
CP[18:0] CPEP
CP[18:0] + 0x1 TPEP
CP[18:0] + 0x2 TCEP
CP[18:0] + 0x3 EMEP
CP[18:0] + 0x4 EIEP
CP[18:0] + 0x5 ICEP
CP[18:0] + 0x6 IMEP
CP[18:0] + 0x7 IIEP
Table 2-26. External Port TCBs for Circular Scatter/Gather DMA
Address Register
CP[18:0] CPEP
CP[18:0] + 0x1 ELEP
CP[18:0] + 0x2 EBEP
CP[18:0] + 0x3 TPEP
CP[18:0] + 0x4 TCEP
CP[18:0] + 0x5 EMEP
CP[18:0] + 0x6 EIEP
CP[18:0] + 0x7 ICEP
CP[18:0] + 0x8 IMEP
CP[18:0] + 0x9 IIEP
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