ADSP-2146x External Port Registers
A-20 ADSP-214xx SHARC Processor Hardware Reference
5–4 EPBR External Port Bus Priority.
00 = Priority order from highest to lowest is SPORT, external
port DMA, core
01 = Priority order from highest to lowest is external port
DMA, SPORT, core
10 = Highest priority is core. SPORT and external port DMA
are in rotating priority
11 = Rotating priority (default)
7–6 DMAPR External Port DMA Channel Priority.
00 = Reserved
01 = EP DMA channel 1 high priority
10 = EP DMA channel 0 high priority
11 = Rotating priority (default)
10–8 FRZDMA Arbitration Freezing Length for DMA.
000 = No Freezing
001 = 4 Accesses
010 = 8 Accesses
011 = 16 Accesses
100 = 32 Accesses
101 = Page size (DDR2 only
1
)
110, 111 = Reserved
11 Reserved
14–12 FRZCR Arbitration Freezing Length for CORE Accesses.
000 = No Freezing
001 = 4 Accesses
010 = 8 Accesses
011 = 16 Accesses
100 = 32 Accesses
101 = Page size (DDR2 only
1
)
110, 111 = Reserved
18–15 Reserved
Table A-8. EPCTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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