ADSP-214xx SHARC Processor Hardware Reference A-19
Registers Reference
Figure A-6. EPCTL Register
Table A-8. EPCTL Register Bit Descriptions (RW)
Bit Name Description
0B0SDSelect Bank 0 DDR2/SDRAM.
0 = Bank 0 non-DDR2
1 = Bank 0 DDR2
1B1SDSelect Bank 1 DDR2.
0 = Bank 1 Non-DDR2
1 = Bank 1 DDR2
2B2SDSelect Bank 2 DDR2 DRAM.
0 = Bank 2 Non-DDR2
1 = Bank 2 DDR2
3B3SDSelect Bank 3 DDR2 DRAM.
0= Bank 3 Non-DDR2
1= Bank 3 DDR2
B0SD
Bank 0 DDR2 DRAM
B1SD
Bank 1 DDR2 DRAM
B2SD
Bank 2 DDR2 DRAM
B3SD
Bank 3 DDR2 DRAM
DMAPR (7–6)
DMA Channel Priority for CH0 and CH1
EPBR (5–4)
External Port Bus Priority
FRZDMA (10–8)
Arbitration Freezing Length for DMA
FRZCR (14–12)
Arbitration Freezing Length for
CORE Accesses
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
FRZSP (21–19)
Arbitration Freezing
Length for SPORT DMA
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