Analog Devices SHARC ADSP-214 Series - Page 1166

Index
I-8 ADSP-214xx SHARC Processor Hardware Reference
enable
DMA interrupt (INTEN) bit, 15-26
EXT_CLK mode, 16-15
external cock synchronization, PCG,
14-20
external port (asynchronous memory
interface), A-22, A-48
multichannel mode in SPORTs, A-170
PCGs, 14-19
peripheral timer, 16-4, 16-21
pin buffer, timer, 16-3
pulse width modulation groups, 7-20
PWM_OUT mode, 16-8
SPIDS
(ISSEN) bit, 15-26
synchronize (counter) bits, PWM, 7-25
WDTH_CAP mode, 16-12
enable receive buffer full interrupt (ERBFI)
bit, A-246
enable transmit buffer empty interrupt
(ETBEI) bit, A-246
endian format, 15-2, A-153
equation
duty cycles in PWM, 7-10
FIR throughput, 6-47
frame sync frequency, 10-9
frame sync pulse (SPORT), 10-9
peripheral timer period, 16-11
pulse width modulation switching
frequency, 7-6
SDRAM clock, 3-34
SDRAM refresh rate, 3-33
serial clock frequency, 10-9
serial port clock divisor, 10-9
SPI clock baud rate, A-239
errors
internal bus (SDRAM), 3-44, 3-80
SPORT error control register, A-172
TWI master mode, 21-21, 21-23
TWI repeat start, 21-24
TWI slave transfer, 21-11, 21-20
errors (continued)
UART baud rate, 20-5
UART sampling, 20-11
event flags, RTC, 18-14
examples
bypass mode (PLL), 22-18
capacitor placement, 23-36
chain assignment, DMA, 2-34
clock post divider, 22-14
edge-aligned PWM, 7-18
external port DMA read, 3-43, 3-78
FIR filter loop, 3-97
multibank SDRAM with data packing,
3-36, 3-73
multiple processor system, 3-39, 3-76
pin buffer, 9-7
power management, 22-12
PWM deadtime, 7-12
PWM emergency dead time, 7-16
PWM switching frequencies, 7-7
read optimization,
3-42, 3-
78
reset generator, 23-42
SDRAM clock, 3-33
single processor system, 3-39, 3-76
SPI interface with AD1855 DAC, 15-10
SRU connections, 9-20 to 9-24
timing for a SPORT multichannel
transfer, 10-34
token passing, 4-11
VCO, 22-15
examples, timing
link port handshake, 4-7
SPI clock, 15-17
SPI transfer protocol, 15-15
SPORT framed vs. unframed data, 10-28
SPORT normal vs. alternate framing,
10-28
exception interrupt, 9-32
EXT_CLK (external event watchdog)
mode, 16-5
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