Analog Devices SHARC ADSP-214 Series - Page 1164

Index
I-6 ADSP-214xx SHARC Processor Hardware Reference
DDR2 bits (continued)
disable DDCKE signal (DIS_DDCKE),
A-26
disable SHARC DLL (SH_DLL_DIS),
A-26
exit self refresh (SREF_EXIT), A-28
external data path width (X16DE), A-27,
A-41, A-42, A-43, A-44
force auto refresh (FARF), A-28
force DLL calibration (ForceDLLcal),
A-27
force EMR2 register write (FEMR2),
A-27
force EMR3 register write (FEMR3),
A-27
force EMR register write (FEMR), A-28
force MR register write (FLMR), A-28
force precharge (Force PC), A-28
pipeline enable (DDR2BUF), A-28
power-up sequence start (DDR2PSS),
A-27
read modify (DDR2MODIFY), A-29
read optimization enable (DDR2OPT),
A-29
row address width (DDR2RAW), 3-62,
A-27, A-43
self refresh mode (DDR2SRF), A-28
DDR2 commands
force load mode register, 3-52
DDR2 registers
control (DDR2CTL0), 3-51, 3-57, 3-60,
A-25
dead time example (PWM), 7-16
debug, 10-60, 23-33
DAI use in, 9-10, 9-40
data buffer use in, 2-11
FIR, 6-45
SPI, 4-21, 15-27, 15-28
SPORT, 10-53
tools use in, 1-5
decimation, FIR, 6-38
destination address, 2-22
DIFS (data independent frame sync select)
bit, A-155, A-159
digital applications interface. See DAI
digital loopback mode, See peripheral
specific loopback mode
digital peripheral interface,
See DPI
DIV
EN (PLL divider enable) bit, 22-15,
A-8, A-10, A-14, A-16
divisor, UART, 20-4, A-249
divisor (DIVx) registers, 10-8, 10-11
DIVx (divisor) registers, A-151
DLAB (divisor latch access) bit, A-243
DMA
access, granting, 2-31
arbitration, 2-44
base registers, 2-8
booting, 2-23
bus priority, 2-42
chained, FFT, 2-18
chained, FIR, 2-16
chained, IIR, 2-17
chained, link port, 2-15
chained, SPI, 2-14
chained, SPORT, 2-14
chained, UART, 2-15, 20-14
chaining, 2-23, 2-32 to 2-36
chaining enable bit (CHEN), 2-34
chain insertion mode, 2-36
chain loading priority, 2-35
chain pointer registers, 2-7, 2-11
channel, buffer registers, listed, 2-36
channel, parameter registers, 2-36
channel allocation, 2-3, 2-36
channel arbitration, 2-36
channel paths, 2-25
channel priority, 2-30
channel priority, external port, 2-43,
A-20, A-46
www.BDTIC.com/ADI