ADSP-2146x External Port Registers
A-28 ADSP-214xx SHARC Processor Hardware Reference
18 (WO) DDR2SRF Self-Refresh Mode.
0 = No effect
1 = Enters sel-refresh mode
19 DDR2ORF Auto-Refresh Command. If this bit is set, the auto-refresh
command is not issue to the DDR2 memory. This mode allows
data streaming connection to FPGA were the refresh is not
required.
0 = Auto-refresh command occurs when refresh counter
expires.
1 = Auto-refresh not performed
20 (WO) FARF Force Auto-Refresh. This bit allows programs to explicitly trig-
ger an auto-refresh command. To use this bit requires that bit
21 is also set, otherwise the DDR2 may crash.
0 = No effect
1 = Force auto-refresh
21 (WO) FPC Force Precharge All. This bit allows programs to explicitly trig-
ger a PREA command.
0 = No effect
1 = Force precharge
22 (WO) FLMR Force Load Mode Register. Forces MR only if the banks are all
precharged.
0 = No effect
1 = Force MR register write to DDR2
23 (WO) FEMR Force EMR Register Write. Forces EMR only if the banks are
all precharged.
0 = No effect
1 = Force EMR register write to DDR2
24 DDR2BUF Enable Pipeline. Enabled this bit if the nominal capacitive
load is exceeded by connecting DDR2 chips in parallel
(4 x IO4).
0 = Disable
1 = External DDR2 control/address buffer enable
25 (WO) SREF_EXIT Self-Refresh Exit.
Table A-11. DDR2CTL0 Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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