ADSP-214xx SHARC Processor Hardware Reference I-5
Index
DAI (continued)
DAI interrupt falling edge
(DAI_IRPTL_FE) register, 11-27
DAI interrupt rising edge
(DAI_IRPTL_RE) register, 11-27
DAI_IRPTL_FE register
as replacement to IMASK, 9-39
DAI_IRPTL_H register, 11-23
DAI_IRPTL_H register as replacement
to IRPTL, 9-39
DAI_IRPTL_L register as replacement
to IRPTL, 9-39
DAI_IRPTL_PRI register, 9-39, 11-27
DAI_PIN_STAT register, A-148
DAI_STAT register, 11-22, A-182,
A-183
edge-related interrupts, 9-37
interrupt controller, 9-32 to 9-38
interrupt controller registers, A-149
interrupts, 9-33
ping-pong DMA status
(SRU_PINGx_STAT) register,
A-182, A-183
pin status (DAI_PIN_STAT) register,
A-148
routing, 9-20
rules for routing, 9-20
selection group E (miscellaneous signals),
A-140
SPORT SRU signal connections, 10-5
status (DAI_STAT) register, A-182,
A-183
system configuration, sample, 9-42
system design, 9-4
DAI_IRPTL_RE register
as replacement to IMASK, 9-39
DAI registers
pin status (DAI_PIN_STAT), A-230
data
buffer, FIR, 6-33
direction control (SPTRAN) bit, A-157,
A-160, A-165
type select (DTYPE) bit, A-153, A-163
data-independent frame sync, 10-20
(DIFS) mode, 10-20
data memory, FFT, 6-6
data ready (DR) status flag (UART), 20-11
data type
and companding, 10-14
and formatting (non-multichannel),
10-22
data words
single word transfers, 10-43
transferring, 10-26
, 10
-36
UART, 20-10
DDR2, 3-46 to 3-83
16-bit address mapping, 3-63 to 3-66
addressing (16-bit, interleaving), 3-65
bank address, 3-27, 3-62
commands, 3-51
DDR2 DLL description, 3-48
decoding address bank, 3-27, 3-62
delay generation, 3-50
interleaving, 3-60
latency, 3-52, 3-54, 3-55, 3-129
memory chip select pins (DDR2_CSx),
3-46
throughput, 3-10, 3-118
DDR2 bits
address mode (ADDRMODE), 3-60
auto refresh (DDR2ORF), A-28, A-43
bank count, 4 or 8 (DDR2BC, A-26,
A-41, A-42
column address width (DDR2CAW),
3-62, A-26
disable access (DIS_DDCTL), A-26
disable clock and control
(DIS_DDCLK1), A-26
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