ADSP-214xx SHARC Processor Hardware Reference 3-83
External Port
Force Load Mode Register
Programs can use the Force LMR command by setting bit 22 (=1) in the
DDR2CTL0 register. The Force LMR bit allows changes to the MODE register
based settings during runtime. These settings include bit 22 (=1) for MR
command (settings DDR2CTL2 register).
Force Auto-Refresh
Bit 20 (=1) in the DDR2CTL0 register forces the auto refresh to be immedi-
ately executed (not waiting until the refresh counter has expired). This is
useful for test purposes but also to synchronize the refresh time base with a
system relevant time base.
Force Extended Mode Register 1–3
Programs use the Force extended mode register 1–3 commands (DDR2CTL0
register) by setting:
bit 23 (=1) for EMR1 command (settings DDR2CTL3 register)
bit 12 (=1) for EMR2 command (settings DDR2CTL4 register)
bit 17 (=1) for EMR3 command (settings DDR2CTL5 register)
This allows programs to initialize or change the content of the EMR
register.
Force DLL External Bank Calibration
The last step during power up is the post calibration of the external
DDR2 banks. This command is enabled by setting bit 13 (=1) in the
DDR2CTL0 register. If enabled the DDR2 controller posts 300 dummy reads
for calibration between the internal DDR2 clock and the
DDR2_DQS1-0
pins which are driven during the read. Note the calibration is done sepa-
rately for each assigned external bank.
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