ADSP-2146x External Port Registers
A-26 ADSP-214xx SHARC Processor Hardware Reference
Table A-11. DDR2CTL0 Register Bit Descriptions (RW)
Bit Name Description
0 DIS_DDR2CTL Disable DDR2 Controller. Enable or disable the DDR2 con-
troller. If the controller is disabled, no accesses to external
DDR2 DRAM address spaces occur. All associated control pins
(DDR2_RAS, DDR2_CAS, DDR2_WE, DDR2_CS,
DDR2_ODT except DDR2_CKE) are in their inactive states
and the DDR2 clock is also disabled.
0 = Enable Controller
1 = Disable Controller
This bit should not be set when DDR2 interface is active, it
can be set in self refresh mode to reduce pad power consump-
tion.
1 DIS_DDR2CLK1 Disable DDR2 Clock 1. Used to disable the 2nd output clock
of the controller. By default, both output clocks are driven.
0 = Activate
1 = Disable
3–2 DDR2BC Bank Count 4 or 8 Bank Device.
00 = Reserved
01 = 4 Bank device
10 = 8 Bank device
11 = Reserved
4 DIS_DDR2CKE Precharge Power-Down Mode. If set, the DDR2CKE signal is
deasserted to bring the DDR2 into precharge power-down
mode. Note that memory banks are not refreshed in this mode.
1 = Enter Precharge Power-down Mode
0 = Exit Precharge Power-down Mode
7–5 DDR2CAW Bank Column Address Width.
000 = Page width 256
001 = Page width 512
010 = Page width 1024
011 = Page width 2048
100 = Page width 4096
Other values are reserved
8 SH_DLL_DIS SHARC On-Chip DLL Disable. Bypass on-chip DLL.
0 = Enable SHARC DLL0 and 1
1 = Disable SHARC DLL0 and 1
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