ADSP-214xx SHARC Processor Hardware Reference A-59
Registers Reference
Figure A-26. SDRRC Register
Table A-31. SDRRC Register Bit Descriptions (RW)
Bit Name Description
11–0 RDIV Refresh Divider Count. This 12-bit field defines the
number of SDCLK cycles between to successive
auto-refresh commands.
Note that RDIV=0 setting is illegal.
15–12 Reserved
16 SDROPT SDRAM Read Optimization. If set (=1) enables read
optimization to improve read throughput for core or
external port DMA access.
0 = Disabled
1 = Enabled
Default setting is 1.
20–17 SDMODIFY SDRAM Read Modifier. According to SDROPT bit this
bit should be set to match the DAG or DMA modifier.
0000 = 0
1111 = 15
Default setting is 1.
31–21 Reserved
RDIV (11–0)
Refresh Divider Count
SDROPT
SDRAM Optimization
SDMODIFY(20–17)
Used for Predictive Addressing
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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