ADSP-214xx SHARC Processor Hardware Reference A-185
Registers Reference
Figure A-98. SRCCTLx Register
Table A-96. SRCCTLx Register Bit Descriptions (RW)
Bit Name Description
0 SRCx_HARD_MUTE Hard Mute. Hard mutes SRC 0, 2.
1 = Mute (default)
1SRCx_AUTO_MUTEAuto Hard Mute. Auto hard mutes SRC 0, 2 when non audio is
asserted by the SPDIF receiver.
0 = No mute
1 = Mute (default)
SRCy_ENABLE
SRCy Enable
SRCy_LENOUT (29–28)
SRCy Output Word Length
SRCy_SMODEOUT (27–26)
SRCy Serial Output Format
SRCy_DITHER
SRCy Dither Enable
SRCy Soft Mute Enable
SRCy_SOFTMUTE
SRCy_HARD_MUTE
SRCy Hard Mute Enable
SRCy_AUTO_MUTE
SRCy Auto Hard Mute
Enable (from SPDIF RX)
SRCy_BYPASS
SRCy De-emphasis Filter
SRCy Bypass Mode
SRCy_DEEMPHASIS (23–22)
SRCy_SMODEIN (20–18)
SRCy Serial Input Format
SRCx_HARD_MUTE
SRCx_RESET
SRCx Reset
SRCx Hard Mute Enable
SRCx_AUTO_MUTE
SRCx Auto Hard Mute
Enable (from SPDIF RX)
SRCx_BYPASS
SRCx De-emphasis Filter
SRCx Bypass Mode
SRCx_DEEMPHASIS (20–18)
SRCx_LENOUT (13–12)
SRCx Output Word Length
SRCx_SMODEOUT (11–10)
SRCx Serial Output Format
SRCx_DITHER
SRCx Dither Enable
SRCx_SMODEIN (4–2)
SRCx Serial Input Format
SRC0 Soft Mute Enable
SRCx_SOFTMUTE
15 14 13 12 11 10 9 8 7654 3 210
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
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