ADSP-214xx SHARC Processor Hardware Reference 23-11
System Design
3 DLEN No delay line DMA (cleared = 0)
4 CBEN No circular DMA (cleared = 0)
5 DFLSH Disabled (cleared = 0)
7 WRBEN Disabled (cleared = 0)
8 OFCEN Disabled (cleared = 0)
9 TLEN Disabled (cleared = 0)
12 INTIRT Disabled (cleared = 0)
17–16 DFS Status (cleared = 00)
20 DMAS Status (cleared = 0)
21 CHS Status (cleared = 0)
22 TLS Status (cleared = 0)
23 WBS Status (cleared = 0)
24 EXTS External access pending (set = 1)
25 DIRS Status (cleared = 0)
Table 23-5. Parameter Initialization for External Port Boot
Parameter Register Initialization Value Comment
IIEP0 IVT_START_ADDR Start of block 0
IMEP0 0x1
ICEP0 0x180
384
× 32-bit transfers
EIEP0 0x4000000 External memory select 1 start address
EMEP0 0x1
ECEP0 0x180
384
× 32-bit transfers
Table 23-4. DMAC0 Boot Settings (0x1000001) (Cont’d)
Bit Name Setting
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