ADSP-214xx SHARC Processor Hardware Reference 3-47
External Port
• Supports 4 and 8 bank DDR2 devices
• Variable memory address map (bank or page interleaving)
• Supports a maximum of 2G bit through the external DDR2 bank
(64M words x 32)
• Supports up to 254M words of DDR2 memory
• Burst mode of 4 (BL = 4) with sequential burst type
• Open page policy—any open page is closed only if a new access in
another page of the same bank occurs
• Supports multibank operation within the DDR2
• Uses a programmable refresh counter to coordinate between vary-
ing clock frequencies and the DDR2’s required refresh rate
• Provides multiple timing options to support additional buffers
between the SHARC-2146x and DDR2
• Supports self-refresh mode and precharge power-down to reduce
power consumption
• Predictive data accesses for higher read data throughput (read
optimization)
• Supports posted CAS additive latency (AL)
• Built in DLL to align DDR2_DATA and DDR2_DQS
• Supports programmable on-die termination (ODT) with the ODT
pin
• Supports external instruction fetch in bank 0 for ISA and VISA
operation
• Supports 64-bit SIMD mode by the core
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