Interrupts
16-18 ADSP-214xx SHARC Processor Hardware Reference
source without reference to the timer’s interrupt signal. The
TMSTAT regis-
ter contains an interrupt latch bit (TIMxIRQ) and an overflow/error
indicator bit (TIMxOVF) for each timer.
These sticky bits are set by the timer hardware and may be watched by
software. They need to be cleared in the TMSTAT register by software explic-
itly. To clear, write a one to the corresponding bit in the TMSTAT register as
shown in Listing 16-1.
Listing 16-1. Clearing Sticky Bits
TMR0_ISR:
ustat2=TIM0IRQ;
dm(TM0STAT)=ustat2; /* W1C the Timer0 bit */
r10=dm(TM0CTL); /* dummy read for write latency */
instructions;
instructions;
RTI;
Interrupt and overflow bits may be cleared simultaneously with
timer enable or disable.
To enable a timer’s interrupt, set the IRQEN bit in the timer’s configuration
(TMxCTL) register and unmask the timer’s interrupt by setting the corre-
sponding bit of the IMASK register. With the IRQEN bit cleared, the timer
does not set its interrupt latch (
TIMxIRQ) bits. To poll the TIMxIRQ bits
without generating a timer interrupt, programs can set the IRQEN bit while
leaving the timer’s interrupt masked.
With interrupts enabled, ensure that the interrupt service routine (ISR)
clears the TIMxIRQ latch before the RTI instruction to assure that the inter-
rupt is not serviced erroneously. In external clock (EXT_CLK) mode, the
latch should be reset at the very beginning of the interrupt routine so as
not to miss any timer event.
To Next Page
Loading...
Need help?
General
