ADSP-214xx SHARC Processor Hardware Reference A-173
Registers Reference
Table A-89. SPERRCTLx Register Bit Descriptions (RW)
Bit Name Description
0DERRA_ENEnable Channel A Error Detection.
0 = Disable
1 = Enable
1DERRB_ENEnable Channel B Error Detection.
0 = Disable
1 = Enable
2FSERR_ENEnable Frame Sync Error Detection.
0 = Disable
1 = Enable
3Reserved
4 (W1C) DERRA_STAT Channel A Interrupt Status.
SPTRAN = 0 Receive overflow status
SPTRAN = 1 Transmit underflow status
5 (W1C) DERRB_STAT Channel B Interrupt Status.
SPTRAN = 0 Receive overflow status
SPTRAN = 1 Transmit underflow status
6 (W1C) FSERR_STAT Frame Sync Interrupt Status.
0 = No frame sync error
1 = Frame sync error detected
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