ADSP-214xx SHARC Processor Hardware Reference 15-25
Serial Peripheral Interface Ports
The
TIMOD (transfer initiation and interrupt) register determines whether
the interrupt is based on the TXSPI or RXSPI buffer status.
If configured to generate an interrupt when SPIRX is full (TIMOD =
00), the interrupt becomes active 1 PCLK cycle after the RXS bit is
set.
During DMA driven transfers, an SPI interrupt is triggered:
1. At the completion of a single DMA transfer when count = 0 and
INTETC = 0, or when the last data is transferred externally and
INTETC = 1.
2. At the completion of a number of DMA sequences (if DMA chain-
ing is enabled).
3. When a DMA error has occurred.
Note that the
SPIDMAC register must be initialized properly to enable DMA
interrupts.
Each of these five interrupts are serviced using the interrupt associated
with the module being used. The primary SPI uses the SPIHI interrupt
and the secondary SPI uses the
SPILI interrupt. Whenever an SPI inter-
rupt occurs (regardless of the cause), the
SPILI or SPIHI interrupts are
latched. To service the primary SPI port, unmask (set = 1) the SPIHI bit
Table 15-7. SPI Interrupt Overview
Interrupt Source Interrupt Condition Interrupt Completion Interrupt
Acknowledge
Default
IVT
SPI (SPI Mode
3–0, 2 channels)
– DMA RX/TX done
– Core RX buffer full
– Core TX buffer empty
– DMA multi master error
– DMA under/overflow error
Internal transfer completion
for core mode of operation.
For DMA modes,
Internal transfer completion
when INTETC = 0.
External transfer completion
when INTETC = 1.
RTI instruction P1I,
P18I
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