Peripherals Routed Through the DPI
A-238 ADSP-214xx SHARC Processor Hardware Reference
2INTENEnable DMA Interrupt on Transfer.
0 = Disable
1 = Enable
3INTETCInterrupt on External Transfer Complete Enable. Selects
interrupt event for transmit DMA
0 = DMA interrupt generated when DMA count reaches zero.
1 = DMA interrupt generated when last bit of last word is
shifted out.
Note: both INTEN and INTETC bits, when enabled, gener-
ate an interrupt for INTETC.
4SPICHENSPI DMA Chaining Enable.
0 = Disable
1 = Enable
6–5 Reserved
7 (WOC) FIFOFLSH DMA FIFO Clear. Clears the SPIS bit.
0 = Disable
1 = Enable
8INTERREnable Interrupt on Error.
0 = Disable
1 = Enable
9 (RO) SPIOVF Receive OverFlow Error (SPIRCV = 1).
0 = Successful transfer
1 = Error – data received with RXSPI full
10 (RO) SPIUNF Transmit Underflow Error (SPIRCV = 0).
0 = Successful transfer
1 = Error occurred in transmission with no new data in TXSPI
11 (RO) SPIMME Multimaster Error.
0 = Successful transfer
1 = Error during transfer
13–12 (RO) SPIS DMA FIFO Status.
00 = FIFO empty
11 = FIFO full
10 = FIFO partially full
01 = Reserved
Table A-123. SPIDMAC, SPIDMACB Register Bit Descriptions
(RW) (Cont’d)
Bit Name Description
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