Analog Devices SHARC ADSP-214 Series - Page 1179

ADSP-214xx SHARC Processor Hardware Reference I-21
Index
refresh rate in SDRAM, 3-33
register drawings, reading, A-2
registers, See peripheral specific registers
register writes and effect latency, SPORTs,
10-40
reset
generators, 23-41
RESET
after power-up, 23-3
RESET
pin, 23-34
input hysteresis, 23-34
resolution (PWM), 7-23
restrictions
external memory access, 3-132
interrupts, B-3
SDRAM, 3-27
SPORTs, 10-32
right justified mode, C-5
right-justified mode
SRC, 12-9
SRC, timing, 12-9
rotating DMA priority, 2-44
ROVF_A or TUVF_A (channel A error
status) bit, A-158, A-161
ROVF_A or TUVF_A (serial port error
status) bits, A-158, A-161
ROVF_B or TUVF_B (channel B error
status) bit, A-157, A-161, A-166
RS-232 device, restrictions, 10-12
RTC
alarm, 18-7
alarm clock features, 18-7
block diagram, 18-8
calibration, 18-2, 18-8
clocking, 18-3
clock register (RTC_CLOCK), 18-3
clock requirements, 18-3
counters, 18-4
digital watch, 18-5
digital watch features, 18-1
disabling, 18-3
RTC (continued)
error, 18-8
event flags, 18-14, 18-15
flags (list), 18-15
initialization register (RTC_INIT), 18-3
pin descriptions, 18-3
pins, 18-3
power-up, 18-4
programming, 18-12
registers, 18-3
reset, 18-4
specifications, 18-1
status register (RTC_STAT), 18-3
stopwatch, 18-8
stopwatch function, 18-8
RTC_ALARM (RTC alarm) register,
18-7
RTC ala
rm (RTC_ALARM) register, 18-7
RTC_STAT (RTC status) register, 18-14
RTC status (RTC_STAT) register, 18-14
RTC stopwatch count (RTC_SWCNT)
register, 18-8
RTC_SWCNT (RTC stopwatch count)
register, 18-8
running reset, 23-4
RXFLSH (flush receive buffer) bit, 15-35,
15-36, 15-38
RXS_A (data buffer channel B status) bit,
A-158, A-161, A-166
RXSPI, RXSPIB (SPI receive buffer)
registers, 15-20, 15-26
RXSPx (serial port receive buffer) registers,
2-10
RXSR (SPI receive shift) register, 15-8
RXS (SPI data buffer status) bit, A-241
RX_UACEN (DMA receive buffer enable)
bit, 20-5
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