Functional Description
12-6 ADSP-214xx SHARC Processor Hardware Reference
The FIFO receives the left and right input data and adjusts the amplitude
of the data for both the soft muting of the SRC and the scaling of the
input data by the sample rate ratio before storing the samples in RAM.
The input data is scaled by the sample rate ratio because as the FIR filter
length of the convolution increases, so does the amplitude of the convolu-
tion output. To keep the output of the FIR filter from saturating, the
input data is scaled down by multiplying it by (SRCx_FS_OP)/(SRCx_FS_IP)
when
SRCx_FS_OP < SRCx_FS_IP. The FIFO also scales the input data to
mute and stop muting the SRC.
The RAM in the FIFO is 512 words deep for both left and right channels.
An offset of 64 to the write address, provided by the SRCx_FS_IP counter,
is added to prevent the RAM read pointer from overlapping the write
Figure 12-1. Sample Rate Converter Block Diagram
SERIAL INPUT
PORT (SIP)
SMODE IN
DE-EMPHASIS
FILTER
SAMPLE RATE
CONVERTER
(SRC) RATIO
SERIAL
OUTPUT
PORT (SOP)
DITHER
MATCHED PHASE
SMODE OUT
64-BIT
SHIFT
REG
64-BIT
SHIFT
REG
PCLK/4
MUTE
IN
MUTE
OUT
SRCx_CLK_IP_I
SRCx_FS_IP_I
SRCx_DAT_IP_I
SRCx_TDM_IP_O
SRCx_TDM_OP_I
SRCx_CLK_OP_I
SRCx_FS_OP_I
SRCx_DAT_OP_O
S/PDIF RX
SRCCTL MUTE
Hard/Soft/Auto
SRCMUTE
Auto/Manual
INTERRUPT
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