Peripherals Routed Through the DPI
A-234 ADSP-214xx SHARC Processor Hardware Reference
6Reserved
8–7 WL Word Len g th. SPI port can transmit and receive three word widths:
00 = 8 bits
01 = 16 bits
10 = 32 bits
8-bit word. SPI port sends out only the lower eight bits of the word written to
the SPI buffer. For example when receiving, the SPI port packs the 8-bit word
to the lower 32 bits of the RXSPI buffer while the upper bits in the registers are
zeros. This code works only if the MSBF bit is zero in both the transmitter and
receiver, and the SPICLK frequency is small. If MSBF = 1 in the transmitter
and receiver, and SPICLK has a small frequency, the received words follow the
order 0x12, 0x34, 0x56, 0x78.
16-bit word. When transmitting, the SPI port sends out only the lower 16 bits
of the word written to the SPI buffer.
When receiving, the SPI port packs the 16-bit word to the lower 32 bits of
the RXSPI buffer while the upper bits in the register are zeros.
32-bit word. No packing of the RXSPI or TXSPI registers is necessary as the
entire 32-bit register is used for the data word.
9MSBF Most Significant Byte First.
0 = LSB sent/received first
1 = MSB sent/received first
10 CPHASE Clock Phase. Selects the transfer format.
0 = SPICLK starts toggling at the middle of 1st data bit
1 = SPICLK starts toggling at the start of 1st data bit (default setting)
11 CLKPL Clock Polarity.
0 = Active high SPICLK (SPICLK low is the idle state)
1 = Active low SPICLK (SPICLK high is the idle state)
Note that the CLKPL/CPHASE bits define the SPI mode.
12 SPIMS SPI Master Select. Configures SPI module as master or slave.
0 = Device is a slave device
1 = Device is a master device
Table A-122. SPICTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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