Index
I-16 ADSP-214xx SHARC Processor Hardware Reference
MCM, multichannel mode, See SPORTs
modes, multichannel mode
media local bus See MLB
memory
coefficient, 6-33
data transfer, FIFO, 11-14
FFT data, 6-6
IIR related, 6-60
mapped IOP (RXSPI and TXSPI) buffer
registers, 15-26
memory-mapped registers, A-2
TCB allocation for DMA, 2-32
transfer types, 2-2
memory select (flags) programming
(MSEN) bit, A-5
memory transfer types, 2-1
microcontroller, host, 23-7
MISCAx_I (signal routing unit external
miscellaneous) register, 14-13
miscellaneous external port parameter
registers, 2-9
miscellaneous signal routing
(SRU_EXT_MISCx) registers (Group
E), A-138
MISOx pins, 15-8, 15-14
MLB
big-endian, 8-8
buffer local channel, 8-8
buffers, 8-9
channel address, 8-6
clock rate, 8-3
configuring circular buffered DMA, 8-17
configuring I/O mode using interrupts,
8-16
configuring ping-pong DMA, 8-17
data structure, 8-7
data transfer, core, 8-8
DMA transfers, 8-11
features, 8-3
frame synchronization, 8-7
MLB (continued)
Generic Synchronous Packet Format
(GSPF), 8-7
interrupts, 8-14
I/O mode transfers, 8-9
I/O service requests, 8-9
little-endian, 8-8
logical channel, 8-6
loop-back testing, 8-14
MLBCLK pin, 8-3
MLBDAT pin, 8-3
MLBSIG pin, 8-3
MOST25 and MOST50, 8-2
multi-packet buffering, 8-12
PICR programming, 8-14
ping-pong DMA, 8-
11
register descriptions, 8-4
registers, A-94 to A-113
RxStatus byte, 8-6
single-packet buffering, 8-12
specifications, 8-1
MLB bits
buffer current address (BCA), 8-10,
A-112
bufferdepth (BD), A-113
buffer final address (BFA), 8-10, A-112
buffer ready, DMA (RDY), A-111
buffer threshold (TH), 8-9, A-113
channel enable (CE), A-107
channel type select (CTYPE), A-107
frame synchronization channel disable
(FSCD), 8-7, A-105
frame synchronization enable (FSE), 8-7,
A-106
frame synchronization physical channel
count (FSPC), A-105
little-endian mode (MLE), 8-8, A-95
loop-back mode (LBM), 8-16
MASK, 8-7
next buffer end address (BEA), A-112
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