8-2 ADSP-214xx SHARC Processor Hardware Reference
The MLB module in the ADSP-214xx serves as an interface between the
MediaLB and ADSP-214xx, implementing the requirements of the physi-
cal layer and the link layer outlined in the MediaLB specification. It
supports up to 31 logical channels with up to 124 bytes of data per Medi-
aLB frame. Transmit and receive data can be transferred between
MediaLB and on-chip memory with single word core-driven transfers or
with DMA block transfers.
The MLB interface on supports MOST25 and MOST50 data
rates. Isochronous modes of transfer are not supported.
Protocol
Master Capable No
Slave Capable Yes
Transmission Simplex Yes
Transmission Half Duplex Yes
Transmission Full Duplex No
Access Type
Data Buffer Yes
Core Data Access Yes
DMA Data Access Yes
DMA Channels 31
DMA Chaining No
Interrupt Source Core/DMA
Boot Capable No
Local Memory Yes
Clock Operation 50 MHz
Table 8-1. MLB Specifications (Cont’d)
Feature Availability
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