Peripheral Registers
A-106 ADSP-214xx SHARC Processor Hardware Reference
16 MASK0 Mask Protocol Error. When set, masks protocol error channel inter-
rupts for this logical channel. This bit valid for all Rx channel types.
This is valid for asynchronous and control Tx channels only.
17 MASK1 Mask Detect Break. When set, masks detect break channel interrupt
for this logical channel. This bit is valid for asynchronous and con-
trol channels only.
18 MASK2
(I/O)
Masks Receive Service Request. When set, masks Rx channel service
request interrupts for this logical channel.
18 MASK2
(DMA)
Mask Buffer Done. When set, masks buffer done channel interrupts
for this logical channel.
19 MASK3
(I/O)
Masks Transmit Service Request. When set, masks Tx channel ser-
vice request interrupts for this logical channel.
19 MASK3
(DMA)
Mask Buffer Start. When set, masks buffer start channel interrupts
for this logical channel.
20 MASK4 Mask Buffer Error. When set, masks buffer error channel interrupts
for this logical channel.
21 MASK5 Reserved
22 MASK6 Mask Lost Frame Synchronization. When set, masks lost frame syn-
chronization channel interrupts for this logical channel.
23 MASK7 Reserved
24 Reserved
26–25 MDS Channel x Mode Select.
00 = Ping-pong DMA mode (default)
01 = Circular buffering DMA
10 = I/O mode enable
11 = Reserved
27 FSE Frame Synchronization Enable. When set, enables streaming chan-
nel frame synchronization for this logical synchronous channel.
Table A-67. MLB_CECRx Register Bit Descriptions for Synchronous
Channels (RW)
Bit Name Description
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