Data Transfer
8-12 ADSP-214xx SHARC Processor Hardware Reference
For ping-pong DMA mode, transmit and receive for all data types are
handled in the following manner.
• At the start of buffer processing, the beginning of the next buffer
becomes the beginning of the current buffer, as the
BSA bits from
the MLB_CNBCRx register are loaded into the BCA bit field of the
MLB_CCBCRx register. Additionally, the end of the next buffer
becomes the end of the current buffer, as the BEA bit field from the
MLB_CNBCRx register is loaded into the BFA bit field of the
MLB_CCBCRx register.
• A current buffer start interrupt is generated (STS bit in the
MLB_CSCRx register), which informs the software that hardware has
updated the MLB_CCBCRn register, cleared the local channel RDY bit,
and is available to accept the next buffer. Software may then pre-
pare the next buffer by writing: BSA, BEA, and RDY bits.
• During the processing of the current buffer, BCA bits continue to
mark which quadlet of data or packet is currently being processed.
• A current buffer done interrupt is generated when the last quadlet
in the current buffer has been successfully transmitted/received.
The current buffer and the next buffer can be configured for either
multi-packet or single-packet buffering, when receiving and transmitting
asynchronous and control packet data.
• Multi-packet buffering allows the system to reduce the interrupt
load at the expense of larger DMA buffers.
• Single-packet buffering allows DMA buffer size to be reduced at
the expense of increasing the interrupt rate.
For more information, see “Programming Model” on page 8-16.
To Next Page
Loading...
Need help?
General
