Analog Devices SHARC ADSP-214 Series User Manual

ADSP-214xx SHARC Processor Hardware Reference A-5
Registers Reference
Figure A-1. SYSCTL Register
Table A-2. SYSCTL Register Bit Descriptions
Bit Name Description
15–0 The bits are used for controlling core function. Refer to the SHARC Processor Program-
ming Reference.
16 IRQ0EN Flag0 Interrupt Mode.
0 = Flag0 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag0 pin is allocated to interrupt request IRQ0.
17 IRQ1EN Flag1 Interrupt Mode.
0 = Flag1 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag1 pin is allocated to interrupt request
IRQ1.
18 IRQ2EN Flag2 Interrupt Mode.
0 = Flag2 pin is a genera-purpose I/O pin. Permits core writes.
1 = Flag2 pin is allocated to interrupt request
IRQ2.
19 TMREXPEN Flag Timer Expired Mode.
0 = Flag3 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag3 pin output is timer expired signal (TMREXP).
20 MSEN Memory Select Enable. Selects between FLGx/
AMI_MSx/IRQx or
TMREXP. Together with bits 19–18 generate a truth table. Detailed
modes of programming for these bits are given in “Core FLAG Pins
Multiplexing” on page 23-28.
0 = FLAG/
IRQx pins are selected
1 = Enables FLAG2 and 3 (IRQ2 and TIMEXP) as MS2 and 3
IRQ0EN
TMREXPEN
MSEN
Memory Select Enable
Flag3 Mode
Flag0 Mode
IRQ1EN
Flag1 Mode
IRQ2EN
Flag2 Mode
PWM3EN
Pulse Width Modulation Select
PWM2EN
Pulse Width Modulation Select
PWM1EN
Pulse Width Modulation Select
PWM0EN
Pulse Width Modulation Select
EPDATA (23–21)
Data Pin Mode Select
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
PWMONDPIEN
DPI Pins as PWM Signals
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Analog Devices SHARC ADSP-214 Series Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English