Analog Devices SHARC ADSP-214 Series - Page 1181

ADSP-214xx SHARC Processor Hardware Reference I-23
Index
signal routing unit (SRU), 16-6
signals
PWM waveform generation and, 16-10
sensitivity in serial ports, 10-6
serial port, 10-8, 10-11
SPORT, 10-5
timer, 16-5
single channel double frequencey mode,
13-12
single processor system example, 3-39, 3-76
single rate operations FIR, 6-38
software reset, 23-4
SP1PDN (SPORT1 clock enable) bit,
A-11, A-16
SP3PDN (SPORT3 clock enable) bit,
A-12, A-17
SPCTLx control bit comparison in four
SPORT operation modes, 10-22
SPCTLx control bits for left-justify mode,
10-25
SPCTLx (serial port control) registers,
10-11, 10-12, 10-21
S/PDIF
See also S/PDIF bits; S/PDIF registers
AAC compressed format, 13-17
AC-3 format, 13-17
audio standards, 13-13
biphase encoding, 13-5
block structure, C-11
clock (SCLK) input, 13-5
compressed audio data, 13-16
DTS format, 13-17
frame sync (LRCLK) input, 13-5
MPEG-2 format, 13-17
non-linear audio data, 13-16
output routing, 13-8
pin descriptions, receiver, 13-4
pin descriptions, transmitter, 11-3, 13-3
preambles, C-16
programming guidelines, 13-6
S/PDIF (continued)
serial clock input, 13-6
serial data (SDATA) input, 13-5
single-channel, double-frequencey
format, 13-12
subframe format, C-13
timing, 13-4
two channel mode, 13-12
S/PDIF bits
biphase error (DIR_BIPHASEERROR),
A-208
channel status buffer enable
(DIT_CHANBUF),
A-201
ch
annel status byte 0 A
(DIT_B0CHANL), A-201
channel status byte 0 B
(DIT_B0CHANR), A-201
channel status byte 0 for subframe A
(DIR_B0CHANL), A-208
channel status byte 0 for subframe B
(DIR_B0CHANR), A-208
disable PLL (DIR_PLLDIS), A-206
frequency multiplier (DIT_FREQ),
A-200
lock error (DIR_LOCK), A-205
lock receiver status (DIR_LOCK),
A-208
mute receiver (DIR_MUTE), A-206
mute transmitter (DIT_MUTE), A-200
non-audio frame mode channel 1 and 2
(DIR_NOAUDIOLR), A-207
non-audio subframe mode channel 1
(DIR_NOAUDIOL), A-207
parity biphase error (DIR_BIPHASE),
A-205
parity (DIR_PARITYERROR), A-208
select single channel double frequency
mode channel (DIT_SCDF_LR),
A-200
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