Peripherals Routed Through the DAI
A-208 ADSP-214xx SHARC Processor Hardware Reference
4 (ROC) DIR_LOCK Lock Receiver. When set (=1), the digital PLL of receiver is
locked, the corresponding DIR_LOCK bit is set. This bit
can be polled to detect the DIR_LOCK condition. After
the receiver is locked, the other status bits in DIRSTAT
and the channel status (DIRCHANL/R) registers can be
read. Interrupts can be also used with some status bits.
0 = Receiver not locked
1 = Receiver locked
5 (ROC) DIR_NOSTREAM No Stream Error. Asserted when the AES3/SPDIF stream
is disconnected. When this bit is asserted and the audio
data in the stream is linear PCM, the receiver performs a
soft mute of the last valid sample from the AES3/SPDIF
stream. A soft mute consists of taking the last valid audio
sample and slowly and linearly decrementing it to zero,
over a period of 4096 frames. During this time, the PLL
three-states the charge pump until the soft mute has been
completed. If non-linear PCM audio data is in the
AES3/SPDIF stream when the NOSTREAM bit is
asserted, the receiver sends out zeros after the last valid
sample.
0 = Stream not disconnected
1 = Stream disconnected (default)
6 (ROC) DIR_PARITYERROR Parity Bit. When cleared, (=0), indicates that the
AES3/SPDIF stream was received with the correct parity,
or even parity. When set (=1), indicates that an error has
occurred, and the parity is odd.
0 = No parity error
1 = Parity error
7 (ROC) DIR_BIPHASEERROR Biphase Error. When set (=1), indicates that a bi-phase
error has occurred and the data sampled from the biphase
stream may not be correct.
0 = No biphase error
1 = Biphase error
15–8 Reserved
23–16 DIR_B0CHANL Channel Status Byte 0 for Subframe A.
31–24 DIR_B0CHANR Channel Status Byte 0 for Subframe B.
Table A-110. DIRSTAT Register Bit Descriptions (RO) (Cont’d)
Bit Name Description
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