Index
I-24 ADSP-214xx SHARC Processor Hardware Reference
S/PDIF bits (continued)
serial data input format
(DIT_SMODEIN), A-201
single channel double frequency channel
select (DIR_SCDF_LR), A-205
stream disconnected
(DIR_NOSTREAM), A-208
transmit single channel double frequency
enable (DIT_SCDF), A-200, A-205
transmitter enable (DIT_EN), A-200
validity bit A (DIT_VALIDL), A-201
validity bit B (DIT_VALIDR), A-201
validity (DIR_VALID), A-207
S/PDIF registers
channel A transmit status
(SPDIF_TX_CHSTA), A-202, A-203
channel B transmit status
(SPDIF_TX_CHSTB), A-203, A-204
left channel status for sub-frame A
(DIRCHANL), A-209
receiver status (DIRSTAT), A-206
SRU control, 13-5, 13-8
transmit control (DITCTL), 13-6,
A-199
SPDIF_TX_CHSTA (Sony/Philips digital
interface channel status) register,
A-202, A-203
special IDP registers, A-148
SPEN_A (serial port channel A enable) bit,
A-153, A-159
SPI
See also SPI bits; SPI registers
AD1855 DAC and, 15-10
address, TCB, 15-33
block diagram, 15-8
booting, 23-12, 23-15
boot packing, 23-17
chained DMA, 2-14
chaining, DMA, 15-13, 15-21, 15-23,
15-25, 15-32
SPI (continued)
change clock polarity, 15-29
changing configuration, 15-29
clock phase, 15-14
clock (SPICLK) pin, 15-14
clock (SPICLK) signal, 15-8
configuring and enabling, 15-31
, 15
-33
core transfers, 15-31, 15-32
DMA, switching from transmit to receive
mode, 15-34
examples, timing, 15-17
examples, transfer protocol, 15-15
features, 15-2
functional description, 15-8
interconnections, master-slave, 15-3
interface signals, 15-3
interrupt, 15-24
loopback mode, 15-28
master boot mode, 23-12
master input slave output (MISOx) pins,
15-8
master mode, 15-30
master mode operation, configuring for,
15-30
master out slave in (MOSIx) pins, 15-8
master-slave interconnections, 15-3
operation, master mode, 15-31, 15-33
operations, 15-30
polarity, clock, 15-14, 15-29
receive data (RXSPI) buffer, 15-8, 15-30
registers, A-232
slave boot mode, 23-15
SPIDS
pin, 15-32, A-233
switching from receive to transmit mode,
15-34, 15-35
system, configuring and enabling bits,
A-232
transfer formats, 15-14
transmit data (TXSPI) buffer, 15-8
To Next Page
Loading...
Need help?
General
