Analog Devices SHARC ADSP-214 Series - Page 1183

ADSP-214xx SHARC Processor Hardware Reference I-25
Index
SPI (continued)
transmit underrun error (SPIUNF) bit,
15-26, 15-37, 15-38, A-238
TXFLSH (flush transmit buffer) bit,
15-35, A-236
SPI bits
chained DMA enable (SPICHEN_A and
SPICHEN_B), A-238
chain loading status (SPICHS), A-239
clock phase (CPHASE), A-234
clock polarity (CLKPL), A-234
device select enable (DSxEN), 15-31,
15-33
DMA interrupt enable (INTEN), 15-26
enable interrupt on error (INTERR),
15-26
enable (SPIEN), A-235
FIFO clear (FIFOFLSH), A-238
flush receive buffer (RXFLSH), 15-35,
15-36, A-236
flush transmit buffer (TXFLSH), A-236
get more data (GM), A-233
input slave select enable (ISSEN), 15-26
input slave select (ISSEN), A-233
internal loop back (ILPBK), A-236
low priority interrupt (SPILI), 15-26
master select (SPIMS), A-234
MISO disable (DMISO), A-233
mode fault error (MME), 15-26, 15-27
most significant byte first (MSBF),
A-234
open drain output select (OPD), A-235
packing enable (PACKEN), A-236
program controlled interrupt bit (PCI),
15-13
receive overflow error (SPIOVF), 15-26,
15-37, 15-38
seamless transfer (SMLS), A-236
send zero (SENDZ), A-233
sign extend (SGN), A-236
SPI bits (continued)
word length (WL), A-234
SPICHEN_A and SPICHEN_B (SPI
DMA chaining enable) bits, A-156,
A-160, A-164
SPICLK (SPI clock) pins, 15-14
SPICLK (SPI clock) signal, 15-8
SPICTL (SPI port control) registers, A-232
SPIDMAC (SPI DMA control) register,
15
-21, A-237
SPIDS
(SPI device select) pin, 15-14
SPIDS
status, See ISSS bit
SPI general operations, 15-4, 15-5
SPILI (SPI low priority interrupt) bit,
15-26
SPI master mode operation, 15-30
SPIOVF (SPI receive overflow error) bit,
15-26, 15-37, 15-38
SPIPDN (SPI clock enable) bit, A-11,
A-12, A-17
SPI registers
DMA configuration (SPIDMAC),
15-21, 15-32, 15-34, A-237
flag (SPIFLGx), A-242
interrupt latch (IRPTL), 15-26
interrupt latch/mask (LIRPTL), 15-26
interrupt (LIRPTL), 15-26
receive buffer (RXSPI), 2-10
receive control (SPICTL, SPICTLB),
A-232
RXSR (SPI receive shift), 15-8
SPIBAUD (baud rate) register, A-239
status (SPISTAT), 15-26, 15-37, A-240
status (SPISTAT, SPISTATB), A-240
transmit buffer (TXSPI), 15-30, A-239
TXSR (SPI transmit shift), 15-8
SPISTAT, SPISTATB (SPI status)
registers, A-240
SPIUNF (SPI transmit underrun error) bit,
15-26, 15-37, 15-38
www.BDTIC.com/ADI