Analog Devices SHARC ADSP-214 Series - Page 1184

Index
I-26 ADSP-214xx SHARC Processor Hardware Reference
SPORT bits, 10-33
B channels enable (MCEB), A-171
chained DMA enable (SCHEN), 10-46,
10-47, 10-57
chained DMA enable (SPICHEN),
A-156, A-160, A-164
channel A enable (SPEN_A), A-153,
A-159
channel error status (ROVF_A or
TUVF_A), 10-16, A-158, A-161
clock, internal clock (ICLK), MSTR (I
2
S
mode only), A-154
clock, MSTR (I
2
S mode only), A-159,
A-163
clock rising edge select (CKRE), 10-8
control bit comparison, 10-22
current channel selected (CHNL), A-171
data independent transmit/receive frame
sync (DIFS), A-155, A-159
data type (DTYPE), 10-22
DMA chaining status (DMACHSxy),
A-171
DMA enable (SDEN), A-156, A-160,
A-164
DMA status (DMASxy), A-171
DXS_B (data buffer status), A-157,
A-161, A-166
frame on rising frame sync (FRFS),
10-29, 10-31
FS both enable (FS_BOTH), A-156
internal frame sync select (IFS), A-155,
A-164
internal serial clock (ICLK), 10-8
late frame sync (LAFS), A-155, A-159
loopback mode (SPL), A-170
multichannel frame delay (MFD), A-170
multichannel mode enable (MCEA),
A-170
number of channels (NCH), 10-35
SPORT bits (continued)
number of multichannel slots (NCH),
A-170
operation mode (OPMODE), 10-19,
10-22, 10-23, 10-25, 10-29, 10-31
program controlled interrupt bit (PCI),
10-48, A-167
receive underflow status (ROVF_A or
TUVF_A), A-158, A-161
serial word length (SLEN), 10-25, 10-29,
10-31
SPORT modes
(I
2
S), 10-21
I
2
S (Tx/Rx on left channel first), 10-24
left-justified, 10-24, 10-28, C-5
loopback, 10-54
multichannel, 10-31
standard DSP, 10-24, 10-25, C-2
SPORT registers
channel selection, 10-36
control, 10-22
control (SPCTLx), 10-11, 10-12, 10-21,
10-22
divisor (DIVx), 10-11
multichannel control (SPMCTLxy),
10-23, 10-33
receive buffer (RXSPx), 10-14, 10-15,
10-40, 10-41, C-4
SPCTLx (serial port control), A-151
transmit buffer (TXSPx), 10-14, 10-15,
10-40, C-4
transmit compand (MTxCSx,
MTxCCSx), A-172
SPORTs, 10-60
See also SPORT bits, modes, registers
128-channel TDM, 10-3
address, DMA, 10-46
address, TCB and, 10-56
buffer hang disable (BHD) bit, 10-54
buffers, data, 10-40
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