Analog Devices SHARC ADSP-214 Series - Page 1188

Index
I-30 ADSP-214xx SHARC Processor Hardware Reference
system, 23-33
throughput
IIR, 6-67
THR register empty (THRE) flag, 20-10,
20-12
time division multiplexed (TDM) mode,
10-31, 12-11, C-7
timer, configuring, A-270
timer registers, A-269
timer control (TMxCTL), A-270
timer status (TMxSTAT), A-271
timers, UART, 20-6
timer See peripheral timers, core timer
timing
external memory accesses, 3-5
kernel boot, 23-23
link port handshake, 4-6
PWM, 7-8, 7-9
S/PDIF, 13-4
SPI clock, 15-17
SPI slave, 15-17
SPI transfer protocol, 15-15
SPORT bits, 10-25
SPORT framed vs. unframed data, 10-28
SPORT normal vs. alternate framing,
10-28
SRC, 12-9
TIMOD (transfer initiation mode) bit,
15-26, 15-30
TMRPDN (timer clock enable) bit, A-11,
A-12, A-17
TMSTAT (peripheral timer global status
and control) register, 16-4
TMxCNT (peripheral timer word count)
registers, 16-4, 16-6
TMxCTL (peripheral timer control)
registers, 16-6
TMxCTL (timer control) registers, A-270
TMxPRD (peripheral timer period)
registers, 16-4
TMxSTAT (timer global status and
control) register, A-271
TMxW (peripheral timer width) registers,
16-5
TMxW (peripheral timer word pulse
width) registers, 16-6
token passing, link ports, 4-11
T_PRDHx (timer period) registers, 16-4,
16-6
transfer, data, 2-46
transfer control block, See DMA TCB
transfer control block See DMA
TCB
transfer direction, external port, 2-
24
transfer initiation and interrupt (TIMOD)
mode, 15-26
transmit and receive data buffers
(TXSPxA/B, RXSPxA/B), 10-40
transmit and receive SPORT data buffers
(TXSPxA/B, RXSPxA/B), 10-40
transmit data (TXSPI) buffer, 15-8
transmit shift (TXSR) register, 15-8
TUVF_A (channel error status) bit, A-158,
A-161
TWI controller
architecture, 21-6
block diagram, 21-7
bus arbitration, 21-9
call address, 21-14
clocking, 21-8
error, 21-11, 21-20, 21-24
fast mode, setting, 21-15
programming model, 21-19
start and stop conditions, 21-11
transferring data, 21-8
TWI controller bits
address not acknowledged (TWIANAK),
A-261
buffer write error (TWIWERR), A-262
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