ADSP-214xx SHARC Processor Hardware Reference A-261
Registers Reference
Figure A-150. TWIMSTAT Register
Table A-141. TWIMSTAT Register Bit Descriptions (RO)
Bit Name Description
0TWIMPROG Master Transfer In Progress.
0 = Currently no transfer is taking place. This can occur once a
transfer is complete or while an enabled master is waiting for an
idle bus.
1 = A master transfer is in progress.
1 (W1C) TWILOST Lost Arbitration.
0 = The current transfer has not lost arbitration with another mas-
ter.
1 = The current transfer was aborted due to the loss of arbitration
with another master.
2 (W1C) TWIANAK Address Not Acknowledged.
0 = The current master transfer has not detected a NAK during
addressing.
1 = The current master transfer was aborted due to the detection
of a NAK during the address phase of the transfer.
3 (W1C) TWIDNAK Data Not Acknowledged.
0 = The current master transfer has not detected a NAK during
data transmission.
1 = The current master transfer was aborted due to the detection
of a NAK during data transmission.
TWIMPROG
TWILOST
TWISCLSEN
TWIBUSY
TWISDASEN
TWIANAK
TWIDNAK
TWIWERR
TWIRERR
Master Tx in Progress
Lost Arbitration
Address Not Acknowledged
Data Not Acknowledged
Bus Busy
Serial Clock Sense
Serial Data Sense
Buffer Write Error
Buffer Read Error
09 837564 2114 12 11 101315
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