Programming Model
16-24 ADSP-214xx SHARC Processor Hardware Reference
2. Initialize the period register with the value of the maximum exter-
nal count.
3. Set the
TIMEN bit. This loads the period value in the counter and
starts the count down.
When the period expires, it is reloaded with the period value and
the cycle repeats. Counter counts with each edge of the input wave-
form, asynchronous to PCLK.
When the period expires, IRQ (if enabled) is set and TMR_IRQ is
asserted. An external clock can trigger the Timer to issue an inter-
rupt and wake up an idle processor.
Reads of the count register are not supported in EXT_CLK mode.
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