ADSP-214xx SHARC Processor Hardware Reference 3-19
External Port
internally connected acknowledge signal, as controlled by refresh, or page
miss latency overhead.
A programmable refresh counter is provided which generates background
auto-refresh cycles at the required refresh rate based on the clock fre-
quency used. The refresh counter period is specified with the
RDIV field in
the SDRAM refresh rate control register (“Refresh Rate Control Register
(SDRRC)” on page A-58).
The internal 32-bit non-multiplexed address is multiplexed into:
• SDRAM column address
• SDRAM row address
• Internal SDRAM bank address
Based on the addressing mapping bit (ADDRMODE = 0) the lowest bits are
mapped into the column address, next bits are mapped into the row
address, and the final two bits are mapped into the internal bank address.
If ADDRMODE = 1 the lowest bits are mapped into the column address, next
bits are mapped into the internal bank address and the final bits are
mapped into the row address. This mapping is based on the SDCAW and
SDRAW values programmed into the SDRAM control register.
The SDC uses no burst mode (BL = 1) for read and write operations. This
requires the SDC to post every read or write address on the bus as for
non-sequential reads or writes, but does not cause any performance
degradation.
For read commands, there is a latency from the start of the read command
to the availability of data from the SDRAM, equal to the CAS latency.
This latency is always present for any single read transfer. Subsequent
reads do not have latency.
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