DAI Signal Routing Unit Registers
A-124 ADSP-214xx SHARC Processor Hardware Reference
Figure A-60. SRU_DAT2 Register (RW)
Figure A-61. SRU_DAT3 Register (RW)
Serial Port 5 Data Channel B Input
SPORT5_DB_I (11–6)
Serial Port 5 Data
Channel A Input
SPORT5_DA_I (5–0)
SRC0_DAT_IP_I (17–12)
Sample Rate Converter 2
Data Input Input
SRC2_DAT_IP_I (29–24)
Sample Rate Converter
1 Data Input Input
SRC1_DAT_IP_I (23–18)
SRC0_DAT_IP_I (17–12) (con’t)
Sample Rate Converter 0
Data Input Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
Sample Rate Converter 3 TDM
Output Input
SRC3_TDM_OP_I (29–24)
SRC1_TDM_OP_I (17–12)
SRC2_TDM_OP_I (23–18)
SRC0_TDM_OP_I (11–6)
SRC3_DAT_IP_I (5–0)
Sample Rate Converter 2
TDM Output Input
Sample Rate Converter 1 TDM
Output Input
Sample Rate Converter 0 TDM
Output Input
Sample Rate Converter 3
Data Input Input
SRC1_TDM_OP_I (17–12) (con’t)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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