Functional Description
3-8 ADSP-214xx SHARC Processor Hardware Reference
Figure 3-2 shows a diagram of the external port for the ADSP-2146x pro-
cessor (containing a DDR2 interface).
As shown in the figures, the external port is a fundamental block since
every access in the external memory space is handled by this port. The
AMI or the SDRAM/DDR2 controller modules act as peripherals to the
external world and as such they are responsible for filling the buffers with
data based on the protocol used. The external port also keeps track of the
two DMA channels which can serve as data streams via the external and
internal memory.
Figure 3-1. External Port Functional Block Diagram (SDRAM)
DMA
ARBITER
DMA
0
DMA
1
SDRAM
ARBITER
SDRAM
CONTROLLER
EP CORE BUS
ACK
WR
RD
ADDR
DATA/MSx
IOD1 (EP)
DMA BUS
AMI
CONTROLLER
32
64
RAS
CAS
WE
CKE
CLK
EP IOP
REGISTER
PERIPHERAL
CORE BUS
SPEP (SPORT) BUS
SDA10, DQM
AMI
ARBITER
32
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