ADSP-214xx SHARC Processor Hardware Reference 18-11
Real-Time Clock—ADSP-2147x
• On countdown from a programmable value
• Daily at a specific time
• On a specific day and time
• On a 1 Hz clock failure
• Completion on pending writes to any 1 Hz registers
Service Interrupts
In the service routine the RTC_STAT register should be read to identify the
cause of the interrupt. While reading the status registerthe RTC automat-
ically clears the respective status bit ensuring that the cause has been
cleared before ending the routine.
The RTC can be programmed to provide an interrupt at the completion
of all pending writes to any of the 1 Hz registers (RTC_CLOCK, and
RTC_INIT). Interrupts can be individually enabled or disabled using the
RTC interrupt control register (RTC_INIT). Interrupt status can be deter-
mined by reading the RTC interrupt status register (RTC_STAT).
The RTC interrupt is set whenever an event latched into the RTC_STAT
register is enabled in the RTC_CTL register. The pending RTC interrupt is
cleared whenever all enabled and set bits in
RTC_STAT are read, or when all
bits in RTC_CTL corresponding to pending events are cleared.
Debug Features
The following section provides information on debugging features avail-
able with the watchdog timer.
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