ADSP-214xx SHARC Processor Hardware Reference A-129
Registers Reference
Figure A-65. SRU_FS0 Register (RW)
Figure A-66. SRU_FS1 Register (RW)
Serial Port 2 Frame Sync Input
SPORT2_FS_I (14–10)
Serial Port 0 Frame
Sync Input
SPORT0_FS_I (4–0)
Serial Port 5 Frame Sync Input
SPORT5_FS_I (29–25)
Serial Port 3 Frame
Sync Input
SPORT3_FS_I (19–15) (con’t)
Serial Port 4 Frame
Sync Input
SPORT4_FS_I (24–20)
Serial Port 1 Frame
Sync Input
SPORT1_FS_I (9–5)
SPORT3_FS_I (19–15)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
SRC2_FS_OP_I (29–25)
SRC1_FS_OP_I
(19–15) (con’t)
SRC2_FS_IP_I (24–20)
SRC1_FS_OP_I (19–15)
SRC0_FS_IP_I (4–0)
SRC0_FS_OP_I (9–5)
SRC1_FS_IP_I (14–10)
Sample Rate Converter 2
Frame Sync Output Input
Sample Rate Converter 1
Frame S ync Output Input
Sample Rate Converter 2
Frame S ync Input Input
Sample Rate Converter 0
Frame Sync Input Input
Sample Rate Converter 1
Frame Sync Input Input
Sample Rate Converter 0
Frame S ync Output Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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