FIR Accelerator
6-50 ADSP-214xx SHARC Processor Hardware Reference
1. Program the number of channels in the
FIRCTL1 register using the
FIR_NCH bits (5–1).
2. Configure the TCBs in internal memory with one channel’s TCB
pointing to the next channel’s TCB.
3. Write the first TCB value into the CPFIR register and enable the
accelerator.
The accelerator fetches the first channel’s TCB and, using it as
pointer, pre-fills the delay line and coefficient memory and loads
the FIRCTL2 register to configure the filter parameters correspond-
ing to that channel.
The accelerator then calculates output samples corresponding to
one Window and stores the data back in internal memory.
At the end of the Window the accelerator updates the IIFIR and
OIFIR registers in the TCB of internal memory and moves to the
next channel.
When all the channels are finished and the auto channel iterate
(CAI, bit 9) is set, the accelerator processes the first channel again
and iterates through the channels. If the CAI bit is cleared, the
accelerator waits for core intervention.
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