ADSP-214xx SHARC Processor Hardware Reference 3-133
External Port
4. A one cycle stall is generated whenever an instruction that contains
a conditional external memory access is in the decode stage, where
the evaluation of the condition is dependent on the outcome of the
previous instruction in address stage. It applies to all kinds of con-
ditions except for conditions based on FLAG status. The following
is an example:
f12 = f11+f10;
if eq dm(ext) = r0;
5. The FLUSH CACHE instruction has an effect latency of one instruc-
tion when executing program instructions from internal memory,
and two instructions when executing from external memory.
6. When a new external memory instruction fetch occurs on the pro-
cessor due to a jump from internal to external memory, or after a
cache hit while executing instructions from external memory, there
is one stall cycle present in the fetch1 stage. This stall avoids
resource conflicts at the cache interface.
7. Any sequence of external memory access (read or write) followed
by an IOP access, causes the IOP access to fail. To workaround this
restriction, separate the external memory access and IOP access by
adding a NOP instruction or any other instruction which is not
either an IOP read/write, or an external memory access. Example:
R12 = dm(Ext_mem);
NOP; /* fixes restriction */
R0 = dm(SPCTL2);
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