Programming Model
8-18 ADSP-214xx SHARC Processor Hardware Reference
4. Configure the MLB control register (
MLB_DCCR) with the appropri-
ate settings and enable the MediaLB device.
5. Configure the base address register (MLB_SBCR, MLB_ABCR or
MLB_CBCR) based on the data type configured for the logical
channel.
6. Check for MLB lock using the status bit in the MLB_SSCR register
using polling or interrupt.
7. Configure the MLB_LCBCRx register for channel buffer threshold,
depth and start address.
8. Configure the logical channel using the MLB_CECRx register for
ping-pong or circular buffer DMA mode, transfer direction, chan-
nel type, channel address and also to generate appropriate
interrupts.
9. Configure the MLB_CNBCRx register with the buffer start and end
address.
10.Set the RDY bit in the MLB_CSCRx register to start the DMA.
Hardware automatically the clears the RDY bit ping-pong DMA but
not for circular buffer DMA. Therefore, for circular buffer DMA,
this bit should be cleared manually by the software to stop buffer
processing.
11.An interrupt is generated depending on the bit unmasked in the
MLB_CECRx register. Within the ISR check that the appropriate sta-
tus bit (in the MLB_CSCRx register) is set.
12.Clear all interrupts by writing 0x0000FFFF to the
MLB_CSCRx
register.
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