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Analog Devices SHARC ADSP-214 Series

Analog Devices SHARC ADSP-214 Series
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ADSP-214xx SHARC Processor Hardware Reference xxxiii
Contents
ASYNCHRONOUS SAMPLE RATE CONVERTER
Features ...................................................................................... 12-2
Pin Descriptions ......................................................................... 12-3
SRU Programming ...................................................................... 12-3
Register Overview ....................................................................... 12-4
Clocking ..................................................................................... 12-5
Functional Description ............................................................... 12-5
Serial Data Ports .................................................................... 12-9
Operating Modes ........................................................................ 12-9
TDM Daisy Chain Mode .................................................... 12-10
TDM Input Daisy Chain ................................................ 12-11
TDM Output Daisy Chain ............................................. 12-11
Bypass Mode ....................................................................... 12-12
Matched-Phase Mode (ADSP-21488) .................................. 12-12
Data Format Matched-Phase Mode .................................. 12-14
Group Delay ................................................................... 12-14
Decimation Rate ................................................................. 12-15
Muting Modes ..................................................................... 12-15
Soft Mute ....................................................................... 12-15
Hard Mute ...................................................................... 12-16
Auto Mute ...................................................................... 12-16
Interrupts ................................................................................. 12-16
Debug Features ......................................................................... 12-17
Effect Latency ........................................................................... 12-17
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