Analog Devices SHARC ADSP-214 Series - Page 32

Contents
xxxii ADSP-214xx SHARC Processor Hardware Reference
Standard DMA ............................................................... 11-20
Ping-Pong DMA ............................................................. 11-21
Multichannel DMA Operation ....................................... 11-21
Multichannel FIFO Status .............................................. 11-22
Interrupts ................................................................................. 11-23
Interrupt Acknowledge ........................................................ 11-23
Threshold Interrupts ........................................................... 11-23
DMA Interrupts .................................................................. 11-24
FIFO Overflow Interrupts ................................................... 11-24
Debug Features ......................................................................... 11-25
Status register Debug .......................................................... 11-25
Buffer Hang Disable ........................................................... 11-25
Shadow Registers ................................................................ 11-25
Core FIFO Write ................................................................ 11-26
Effect Latency .......................................................................... 11-26
Write Effect Latency ........................................................... 11-26
IDP Effect Latency .............................................................. 11-26
Programming Model ................................................................. 11-26
Setting Miscellaneous Bits ................................................... 11-27
Starting Core Interrupt-Driven Transfer .............................. 11-27
Additional Notes ............................................................ 11-28
Starting A Standard DMA Transfer ...................................... 11-29
Starting a Ping-Pong DMA Transfer .................................... 11-30
Servicing Interrupts for DMA ............................................. 11-31
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